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开源工具 marktechpost.com · @Asif Razzaq

NVIDIA发布CUDA Rust:cuda-oxide和cutile-rs实现编译时安全的GPU内核

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NVIDIA宣布CUDA Rust,推动Rust成为GPU内核的一等语言,两个开源项目cuda-oxide和cutile-rs分别支持SIMT和Tile编程模型。

AI推荐理由 NVIDIA宣布CUDA Rust,使Rust成为GPU内核的一等语言,对开发者有直接价值,信息具体且来源可靠。

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人工智能 AI基础设施 技术 AI简讯 应用 编辑精选 面向开发者 硬件 机器学习 新发布 员工 科技新闻 NVIDIA宣布了CUDA Rust,旨在推动Rust成为编写GPU内核的一等语言。Rust代码此前已经可以启动CUDA内核,但内核主体通常必须在其他地方编写。CUDA Rust通过两个NVlabs开源项目填补了这一空白:用于SIMT模型的cuda-oxide和用于较新Tile模型的cutile-rs。两者都原生编译Rust内核,并利用Rust的所有权规则在编译时拒绝别名错误。 它是否可部署?部分可部署。cutile-rs已发布在crates.io上,可在稳定版Rust 1.89+上运行,并已用于Hugging Face的Grout推理引擎和mistral.rs。cuda-oxide处于早期alpha阶段。这两个项目都处于alpha阶段,尚未确认可用于生产环境。 为什么在GPU内核中使用Rust AI的系统层,从推理引擎到驱动程序和代理运行时,越来越多地使用Rust编写。NVIDIA的Nova Linux驱动程序使用Rust,NVIDIA Dynamo具有Rust核心,NVTX具有Rust绑定。GPU内核是例外。 这两条轨道反映了CUDA已经提供的两种编程模型。SIMT是CUDA C++和numba-cuda中使用的模型:你描述一个线程做什么,然后启动数千个线程。Tile是较新的模型,也可用于C++和Python:你描述一个数据块做什么,Tile IR编译器处理线程映射和内存布局。NVIDIA建议优先使用Tile,对于显式线程和内存控制则使用SIMT。计划中的跨语言互操作意味着选择Rust不会将开发者排除在C++或Python之外。 SIMT轨道:cuda-oxide cuda-oxide是一个自定义的rustc代码生成后端。它将#[kernel]函数通过Rust MIR、社区Pliron IR框架和LLVM IR路由到PTX,然后将其他所有内容交给标准后端。NVIDIA在Pliron之上编写了GPU方言。 要求:Linux、计算能力8.0或更高版本的GPU、CUDA 12.x或更新版本、带libclang的clang,以及固定的nightly工具链(nightly-2026-04-03)。cargo oxide doctor检查设置,cargo oxide new搭建一个向量加法程序,主机和设备代码位于同一文件中。 安全论证在于内核签名。输入a和b是普通的共享切片。输出c是DisjointSlice,一种为每个线程提供对其自身元素的独占访问的类型。普通的&mut [f32]需要每个线程持有相同的可变借用,Rust会拒绝。c.get_mut(idx)返回一个Option,因此越界访问成为处理过的分支。#[launch_contract]属性声明块形状,生成的prepare_vecadd方法在安全启动运行之前验证启动配置。 Tile轨道:cutile-rs cutile-rs在更高一层工作。每个块将内核主体作为单个逻辑线程在一个子张量上运行一次,编译器决定有多少真实GPU线程支持它。#[cutile::module]宏将内核的AST嵌入主机二进制文件,并在内核首次启动时通过CUDA Tile IR进行JIT编译。 要求更轻:计算能力8.0或更高版本、CUDA 13.3、稳定版Rust 1.89或更新版本,以及Linux,无需nightly和自定义LLVM。设置是cargo new,然后cargo add cutile。 主机端的.partition([128])调用执行三项工作。它赋予每个块对其128元素块的独占所有权,将网格固定为1,024 / 128 = 8个块,并提供常量块宽度B。输入张量使用-1作为在启动时解析的动态维度。生成的启动器获取所有张量的所有权,并在GPU完成时返回它们。在.sync_on(&stream)之前不执行任何操作;之前的一切都是在一个链中记录的惰性描述。 编译器捕获的内容 将SIMT内核的输出缓冲区作为其自身输入之一传递会失败,并显示错误[E0502]:无法将c_dev作为可变借用,因为它也被不可变借用。Tile端的相同别名问题会失败,并显示错误[E0382]:使用已移动的值:z。cuda-oxide检查每次启动调用;cutile-rs的所有权在启动边界上跟踪张量,NVIDIA称这是更强的保证。 Tile不暴露共享内存或线程索引供误用。SIMT保留这种控制,但cuda-oxide中的共享内存目前需要unsafe。 关键要点 CUDA Rust在Rust中增加了两个原生GPU内核轨道:cuda-oxide(SIMT)和cutile-rs(Tile)。 cuda-oxide通过Pliron和LLVM将Rust MIR编译为PTX;它需要固定的nightly版本。 cutile-rs在稳定版Rust 1.89+上运行,使用CUDA 13.3,并通过CUDA Tile IR进行JIT编译。 两者都使用Rust的借用检查器和所有权在编译时拒绝缓冲区别名。 cutile-rs已为Grout和mistral.rs提供支持;两个项目都尚未准备好用于生产环境。 在此处查看技术细节。另外,请随时在Twitter上关注我们,别忘了加入我们的150k+ML SubReddit并订阅我们的新闻通讯。等等!你在telegram上吗?现在你也可以在telegram上加入我们。 需要与我们合作推广你的GitHub仓库或Hugging Face页面或产品发布或网络研讨会等?联系我们 Asif Razzaq 网站 | + 文章简介 Asif Razzaq是Marktechpost Media Inc.的首席执行官。作为一位有远见的企业家和工程师,Asif致力于利用人工智能的潜力促进社会公益。他最近的努力是推出了人工智能媒体平台Marktechpost,该平台以深入报道机器学习和深度学习新闻而著称,这些新闻在技术上可靠且易于广大受众理解。该平台每月浏览量超过200万,显示了其在受众中的受欢迎程度。 Asif Razzaq Google DeepMind发布AlphaGenome Atlas,包含90亿个人类DNA变体的预计算分子效应预测和AVI评分 Asif Razzaq Reducto发布r-1:一种单遍文档解析模型,每页1美分,错误减少20% Asif Razzaq IFM发布K2 Horizon:六个Apache 2.0模型,从0.9B到375B Asif Razzaq H Company发布NeoMME:260M和800M单塔多模态编码器系列,去除了视觉塔和因果解码器 错误减少20%,每页1美分 Asif Razzaq IFM发布K2 Horizon:六个Apache 2.0模型,从0.9B到375B Asif Razzaq H Company发布NeoMME:260M和800M单塔多模态编码器系列,去除了视觉塔和因果解码器
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Artificial Intelligence AI Infrastructure Technology AI Shorts Applications Editors Pick For Devs Hardware Machine Learning New Releases Staff Tech News NVIDIA has announced CUDA Rust, a push to make Rust a first-class language for writing GPU kernels. Rust code could already launch CUDA kernels, but the kernel body usually had to be written elsewhere. CUDA Rust closes that gap with two NVlabs open-source projects: cuda-oxide for the SIMT model and cutile-rs for the newer Tile model. Both compile Rust kernels natively and use Rust’s ownership rules to reject aliasing bugs at compile time. Is it deployable? Partially. cutile-rs is published on crates.io, runs on stable Rust 1.89+, and is already used in Hugging Face’s Grout inference engine and in mistral.rs. cuda-oxide is early alpha. The both projects are in alpha phase and not confirmed for production. Why Rust for the GPU Kernel The systems layer of AI, from inference engines to drivers and agent runtimes, is increasingly written in Rust. NVIDIA’s Nova Linux driver is in Rust, NVIDIA Dynamo has a Rust core, and NVTX has Rust bindings. The GPU kernel was the exception. The two tracks mirror the two programming models CUDA already offers. SIMT is the model used in CUDA C++ and numba-cuda: you describe what one thread does and launch thousands of them. Tile is the newer model, also available in C++ and Python: you describe what one tile of data does, and the Tile IR compiler handles thread mapping and memory layout. NVIDIA recommends Tile first, with SIMT for explicit thread and memory control. Planned inter-language interop means choosing Rust will not lock developers out of C++ or Python. The SIMT Track: cuda-oxide cuda-oxide is a custom rustc codegen backend. It routes #[kernel] functions through Rust MIR, the community Pliron IR framework, and LLVM IR down to PTX, then hands everything else to the standard backend. NVIDIA wrote the GPU dialects on top of Pliron. Requirements: Linux, a GPU with compute capability 8.0 or later, CUDA 12.x or newer, clang with libclang, and a pinned nightly toolchain (nightly-2026-04-03). cargo oxide doctor checks the setup and cargo oxide new scaffolds a vector addition program, with host and device code in one file. The safety argument sits in the kernel signature. Inputs a and b are ordinary shared slices. The output c is a DisjointSlice, a type that gives each thread exclusive access to its own element. A plain &mut [f32] would need every thread to hold the same mutable borrow, which Rust refuses. c.get_mut(idx) returns an Option, so out-of-bounds access becomes a handled branch. A #[launch_contract] attribute declares the block shape, and the generated prepare_vecadd method validates the launch configuration against it before the safe launch runs. The Tile Track: cutile-rs cutile-rs works one level higher. Each tile block runs the kernel body once as a single logical thread over one sub-tensor, and the compiler decides how many real GPU threads back it. The #[cutile::module] macro embeds the kernel’s AST in the host binary and JIT-compiles it through CUDA Tile IR when the kernel is first launched. Requirements are lighter: compute capability 8.0 or later, CUDA 13.3, stable Rust 1.89 or newer, and Linux, with no nightly and no custom LLVM. Setup is cargo new, then cargo add cutile. The host-side .partition([128]) call does 3 jobs. It gives each tile exclusive ownership of its 128-element chunk, fixes the grid at 1,024 / 128 = 8 tiles, and supplies the const tile width B. Input tensors use -1 as a dynamic dimension resolved at launch. The generated launcher takes ownership of all tensors and returns them when the GPU finishes. Nothing executes until .sync_on(&stream); everything before it is a lazy description recorded in one chain. What the Compiler Catches Passing the SIMT kernel’s output buffer as one of its own inputs fails with error[E0502]: cannot borrow c_dev as mutable because it is also borrowed as immutable. The same aliasing on the Tile side fails with error[E0382]: use of moved value: z. cuda-oxide checks each launch call; cutile-rs’s ownership follows tensors across the launch boundary, which NVIDIA calls the stronger guarantee. Tile exposes no shared memory or thread indexing to misuse. SIMT keeps that control, but shared memory in cuda-oxide currently requires unsafe. Key Takeaways CUDA Rust adds 2 native GPU kernel tracks in Rust: cuda-oxide (SIMT) and cutile-rs (Tile). cuda-oxide compiles Rust MIR through Pliron and LLVM to PTX; it needs a pinned nightly. cutile-rs runs on stable Rust 1.89+ with CUDA 13.3 and JIT-compiles via CUDA Tile IR. Both reject buffer aliasing at compile time using Rust’s borrow checker and ownership. cutile-rs already powers Grout and mistral.rs; neither project is production-ready yet. Check out the Technical details here. Also, feel free to follow us on Twitter and don’t forget to join our 150k+ML SubReddit and Subscribe to our Newsletter. Wait! are you on telegram? now you can join us on telegram as well. Need to partner with us for promoting your GitHub Repo OR Hugging Face Page OR Product Release OR Webinar etc.? Connect with us Asif Razzaq Website |  + postsBio Asif Razzaq is the CEO of Marktechpost Media Inc.. As a visionary entrepreneur and engineer, Asif is committed to harnessing the potential of Artificial Intelligence for social good. His most recent endeavor is the launch of an Artificial Intelligence Media Platform, Marktechpost, which stands out for its in-depth coverage of machine learning and deep learning news that is both technically sound and easily understandable by a wide audience. The platform boasts of over 2 million monthly views, illustrating its popularity among audiences. Asif Razzaq Google DeepMind Releases AlphaGenome Atlas With Precomputed Molecular Effect Predictions and AVI Scores for 9 Billion Human DNA Variants Asif Razzaq Reducto Releases r-1: A Single Pass Document Parsing Model That Cuts Errors 20% at 1 Cent Per Page Asif Razzaq IFM Releases K2 Horizon: Six Apache 2.0 Models From 0.9B to 375B Asif Razzaq H Company Releases NeoMME: A Family of 260M and 800M Single-Tower Multimodal Encoders That Drop the Vision Tower and Causal Decoder

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