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AMD 矩阵核心的精确建模
该 arXiv 论文(v2,2026-09-15 修订)针对 AMD CDNA 1、CDNA 2、CDNA 3 架构(对应 MI100、MI210/250、MI300A/300X)的矩阵乘法单元进行数值行为表征,覆盖累加器位宽、舍入行为、归一化点、中间下溢/溢出逻辑、次正规数处理及特殊输入等特性。作者为所有支持的输入格式设计测试向量,并开发各架构的 MATLAB 软件模型,使用 1000 万组随机输入向量验证达到位级可复现。作为概念验证,作者用这些模型在两个数值应用中量化了 AMD 矩阵核心与 NVIDIA tensor cores 的应用级精度差异。
AI推荐理由 arXiv 论文(cs.AR/cs.MS),作者为 Faizan A Khattak、Mantas Mikaitis、Carlo J. Graziani,v2 于 2026-09-15 修订。核心新信息:针对 AMD CDNA 1/2/3(MI100、MI210/250、MI300A/300X)矩阵乘法单元的数值行为进行表征,设计测试向量覆盖所有支持输入格式,并给出基于 MATLAB 的逐架构软件模型,用 1000 万组随机输入向量验证达到位级可复现;还以两个数值应用示例量化 AMD matrix cores 与 NVIDIA tensor cores 的应用级精度差异。价值在于为 GPU 矩阵单元的非 IEEE 754 行为提供可复现建模工具,对数值计算、可复现性和跨厂商对比研究有实际用途。局限:摘要未给出模型开源地址、具体误差数值或第三方复现,位级匹配仅限作者自测;应用级差异结论需看全文验证。
78
正文
Computer Science > Hardware Architecture
arXiv:2609.14845 (cs)
[Submitted on 13 Sep 2026 (v1), last revised 15 Sep 2026 (this version, v2)]
Title:Accurate Models of AMD Matrix Cores
Authors:Faizan A Khattak, Mantas Mikaitis, Carlo J. Graziani
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Abstract:Matrix multipliers available on recent GPUs do not conform with the IEEE 754 floating point standard. Features of matrix multipliers differ across vendors and architectures of the same vendor, such as accumulator width, rounding behaviour, normalisation points, intermediate underflow and overflow logic, the handling of subnormals, and the treatment of special inputs. As a result, reproducibility of small matrix multiplier results across devices is not possible and cannot be achieved by software control. Implementation details of matrix multipliers are not documented, making it difficult to interpret discrepancies in the computed results. We characterise the numerical behaviour of matrix multipliers across three AMD GPU architectures: CDNA 1, CDNA 2, and CDNA 3, using the MI100, MI210/250, and MI300A/300X GPUs, respectively. We design test vectors to target numerical features for all supported input formats and provide the derivation and the reasoning for why each vector allows to determine a particular numerical feature based on the outputs of the devices. MATLAB-based software models of the matrix multipliers are then developed for each architecture and validated for bit-level reproducibility against hardware using a randomized test suite consisting of 10 million sets of random input vectors. To achieve this, we applied a previously developed technique to iteratively refine the accuracy of the models in a loop, by randomized testing followed by test-refinement until the model matches the hardware for every test case. Finally, as a proof of concept for what experimental research can be done with the models, we have utilised them in two demonstrative numerical applications, quantifying application-level accuracy differences between AMD matrix cores and the NVIDIA tensor cores.
Subjects:
Hardware Architecture (cs.AR); Mathematical Software (cs.MS)
Cite as:
arXiv:2609.14845 [cs.AR]
(or
arXiv:2609.14845v2 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2609.14845
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arXiv-issued DOI via DataCite
Submission history
From: Faizan Ahmad Khattak [view email]
[v1]
Sun, 13 Sep 2026 23:34:01 UTC (1,297 KB)
[v2]
Tue, 15 Sep 2026 10:33:08 UTC (1,297 KB)
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