大模型
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面向LLM推理的KV缓存管理策略比较表征
该论文对三种主流 KV 缓存管理框架 vLLM、InfiniGen 和 H2O 进行实证研究,这些框架分别采用张量卸载、token 驱逐启发式和推测调度等技术来平衡内存与性能。作者在请求率、模型规模和稀疏度等关键参数下,评估延迟、吞吐量和内存占用等指标,指出各框架表现最佳的条件,为内存与性能约束下的 KV 缓存策略选择与配置提供依据。
AI推荐理由 arXiv 论文(cs.AR/cs.AI),对 vLLM、InfiniGen、H2O 三种 KV 缓存管理框架做实证对比,覆盖延迟、吞吐、内存占用及请求率、模型规模、稀疏度等参数,并给出各框架最优适用条件。属于可验证的系统性评测,对 LLM 推理部署选型有直接参考价值;局限是仅摘要可见,具体实验数据与结论细节未提供,且为 v2 修订版而非首次发布。
78
正文
Computer Science > Hardware Architecture
arXiv:2604.05012 (cs)
[Submitted on 6 Apr 2026 (v1), last revised 15 Sep 2026 (this version, v2)]
Title:Comparative Characterization of KV Cache Management Strategies for LLM Inference
Authors:Oteo Mamo, Olga Kogiou, Hyunjin Yi, Weikuan Yu
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Abstract:Efficient inference with Large Language Models (LLMs) increasingly relies on Key-Value (KV) caches to store previously computed key and value vectors at each layer. These caches are essential to minimize redundant computation during autoregressive token generation, lowering computational complexity from quadratic to linear. However, the growth of KV caches has posed significant system-level challenges, particularly as model sizes increase, context lengths grow, and concurrent requests compete for limited memory resources. Even though several recent frameworks for KV cache management have emerged, their comparative trade-offs in memory consumption and inference performance have not been fully understood, especially under varying request sizes and model configurations. In this work, we conduct an empirical study of three state-of-the-art KV cache management frameworks: vLLM, InfiniGen, and H2O. These frameworks employ techniques such as tensor offloading, token eviction heuristics, and speculative scheduling to balance memory usage and performance. We evaluate their performance in terms of a range of metrics such as latency, throughput, and memory usage across a spectrum of key parameters including request rates, model sizes, and sparsity levels. Our results pinpoint the conditions for each framework to perform the best, revealing the most suitable selection and configuration of KV cache strategies under memory and performance constraints.
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Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
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arXiv:2604.05012 [cs.AR]
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arXiv:2604.05012v2 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2604.05012
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Submission history
From: Oteo Mamo [view email]
[v1]
Mon, 6 Apr 2026 16:00:39 UTC (9,605 KB)
[v2]
Tue, 15 Sep 2026 16:46:36 UTC (9,605 KB)
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