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SpecLens：基于 LLM 的 Verilog 生成，借助行为差异从规范中导出约束
该论文提出 SpecLens，一个面向 LLM 的 Verilog 生成自动化框架：以原始自然语言规范作为唯一外部语义来源，通过分析多个候选实现之间的行为差异来导出任务特定的规范约束，而非依赖 RAG、自规划或 few-shot 等外部增强。在 VerilogEval v2.0 spec-to-RTL 基准上，SpecLens 使用 o3-mini-medium 达到 86.2% 的功能 pass@1，使用 o3-mini-high 达到 89.4%，分别较 SOTA prompting 方法和 SOTA 行为差异方法提升 3.6 与 3.8 个百分点；在 VerilogEval v2.0 上语法正确率为 100%，RTLLM v1.1 为 86.2%、v2.0 为 88%，且未使用代价高昂的编译-修复迭代循环。作者称在 RTLLM 上分析显示该方法更忠实于规范、更少依赖基准对齐先验，代码已开源。
AI推荐理由 arXiv 预印本，摘要给出明确方法（通过多个候选实现的行为差异从规范中导出约束）与可核验基准结果：VerilogEval v2.0 上 o3-mini-medium 功能 pass@1 达 86.2%、o3-mini-high 达 89.4%，分别较 SOTA prompting 与 SOTA 行为差异方法提升 3.6 和 3.8 个百分点，并报告 RTLLM v1.1/v2.0 的语法正确率，代码开源。局限在于仅为预印本、未经同行评审，且结果依赖 o3-mini 特定配置，未提供跨模型泛化证据。
78
正文
Computer Science > Hardware Architecture
arXiv:2609.16729 (cs)
[Submitted on 15 Sep 2026]
Title:SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Authors:Wen Bing, Bing Li
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Abstract:Large language models (LLMs) have recently shown promise in Verilog generation, but producing functionally correct RTL directly from natural-language specifications remains a highly challenging task. Existing approaches improve LLM-based Verilog generation mainly with retrieval-augmented generation (RAG), self-planning, or few-shot prompting. However, these methods focus primarily on external or generic forms of enhancement rather than strengthening the specification with task-specific constraints. In this work, we propose SpecLens, an automated framework for LLM-based Verilog generation that derives specification-driven constraints by analyzing behavioral divergence among multiple candidate implementations, using the original specification as the only external semantic source during generation. On the VerilogEval v2.0 spec-to-RTL benchmark, SpecLens achieves a functional pass@1 ratio of 86.2\% with o3-mini-medium and 89.4\% with o3-mini-high. This corresponds to a 3.6 percentage-point gain over the SOTA prompting method with o3-mini-medium and a 3.8 percentage-point gain over the SOTA behavioral divergence method with o3-mini-high. In addition, on RTLLM v1.1 and v2.0, analysis shows that SpecLens is more specification-faithful and less prone to benchmark-aligned priors. SpecLens achieves 100\% syntactic correctness on VerilogEval v2.0, 86.2\% on RTLLM v1.1, and 88\% on RTLLM v2.0, even without using costly compile-repair loops to revise generated code iteratively. The code is open source and available at this https URL.
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Hardware Architecture (cs.AR)
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arXiv:2609.16729 [cs.AR]
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arXiv:2609.16729v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2609.16729
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From: Wen Bing [view email]
[v1]
Tue, 15 Sep 2026 06:59:00 UTC (398 KB)
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